sizing components of a 2-input NOR gate with given input capacitance

[anhnha]

Please help me with the question below. Thank you.

 

[erikl]

How did you calculate these propagation delay times? Elmore model? Probably you got a bit longer rising time delay. See the explanation in your Weste-Harris book, chap. 4.2 Delay Estimation, Example Solution, p. 163 in my edition: "Despite the fact that the rise and fall resistances are equal ..." (this is valid for a NAND gate, for a NOR it will be the other way round.

The above sizing is correct for a CMOS process with p-mobility = 1/2 n-mobility.

 

[anhnha]

Thank you. I used Elmore model and as you said, rising delay is longer than falling.
As the explanation from the book, it seems that the components are sized so that the gate has the same rise and fall resistances.

For example, with 2-input NOR above, in the worst case we have:
rise resistance: R/X
fall resistance: 2R/Y + 2R/Y = 4R/Y
Set rise resistance equal:
R/X = 4R/Y
or Y = 4X
In addition, we have X + Y = 15
Therefore, X = 3, Y = 12. That is the correct answer.
I used the same approach for 3-input NAND gate in the book example and the result is totally correct. :grin:
In example 4.13, chapter 4 Delay, the NAND gate has input capacitance of 10C.
The result given:
NMOS size: X = 6
PMOS size: Y = 4

My calculation:
rise resistance: 2R/Y
fall resistance: R/X + R/X + R/X = 3R/X
Set rise and fall resistances equal:
2R/Y = 3R/X
or: 2X = 3Y
In addition, X + Y = 10.
Therefore, X = 6, Y = 4.
That is also correct.