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Sure: from the equation / Q=CV=It / you can get the slew rate at the large transistor's gate δV/δt = I/C .
I is the drive transistor's max. driving current capability, C is the gate input capacitance Cgg of the driven transistor.
This is a 50:1 taper which is abnormal. Best prop delay in
a logic chain is around 3:1, I've done clock trees at 2:1
when pressing against the process speed capability, and
stick to roughly 4:1 for power FET driver taper chains
(or 4:1 "off", 8:1 "on" if I'm doing a "ballistic" anti-shoot-
through design). Never have I been happy with so weak
a gate drive, in a switching circuit.
Though I suppose if you wanted a controlled slew, this
is one way to get it. Not as well controlled, though, as
a stiff driver and a series resistor, in respect to process
and temperature and supply variation.