sunny153 said:Just check the connection, if the connections are swapped then LVS might identifying tran A & B wrongly.
Or if you have the multiple fingures of A & B, check the connections for all the fingers, error can be there also.
foreverloves said:thank you!
the number is correct,
in fact, it is a structure as shown in the attached picture, terminal A and B are connected to differient transistors. the two transitors have differient dimension.
in this case, Cadence can not distinguish the two transitors therefore size error occurs
but the problem is: how to solve it ??
truebs said:hi
the porblem might be because of symetrical nature of your circuit. try to put some label on nets or transistor so that it could resolve ambiguities. However this error does not mean that layout or connection is wrong. You can still proceed if only this error is ther in your layout (infact it must be a warning).
yes, they are connected togetherShohdy said:Hi,
I want to ask if nets A and B are connected to each other as shown in the image above????
Regards,
Shohdy
truebs said:hi
the porblem might be because of symetrical nature of your circuit. try to put some label on nets or transistor so that it could resolve ambiguities. However this error does not mean that layout or connection is wrong. You can still proceed if only this error is ther in your layout (infact it must be a warning).
Shohdy said:can you send the part of netlist that's making the problem????
hello Hughes,Hughes said:Two transistors are connected in parallel. You may add permute rule for parallel mosfets. Then they will be treated as a single device both in layout and in schematic.
If you don't like to combine the parallel devices (since they have different lengths), you may use correspondence points to specify which device in layout should be correspondent to which device in schematic.
sunny153 said:Try to match the ROD name/Instance name of the schematic and layout same for A & B. If not, edit the property of the A & B, and match it as per the schematic. The error might go..
safwatonline said:hello Hughes,Hughes said:Two transistors are connected in parallel. You may add permute rule for parallel mosfets. Then they will be treated as a single device both in layout and in schematic.
If you don't like to combine the parallel devices (since they have different lengths), you may use correspondence points to specify which device in layout should be correspondent to which device in schematic.
can u explain how to do that?
does adding a label in both schematic and layout to one of the transistor will solve this?
thnx alot
foreverloves said:thank you!
the number is correct,
in fact, it is a structure as shown in the attached picture, terminal A and B are connected to differient transistors. the two transitors have differient dimension.
in this case, Cadence can not distinguish the two transitors therefore size error occurs
but the problem is: how to solve it ??
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