"size error" during LVS,urgent, thank you!!!

[foreverloves]

the enviroment is cadence spectre

after LVS, it says the dimension of transistor A should be the dimension of transistor B and vice versa. I checked the layout and found that the dimension
of both A and B are correct

could any other errors indirectly lead to this error??

many thanks!!

 

[sunny153]

Just check the connection, if the connections are swapped then LVS might identifying tran A & B wrongly.

Or if you have the multiple fingures of A & B, check the connections for all the fingers, error can be there also.

 

[foreverloves]

thank you .i do not have multiple fingures .

there are no terminal or net mismatches either.

but in the error report, it says:

"net list ambiguities was resolved by random selection"

what is the problem?

how can Cadence resolve net list problem randomly?

so strange!!!!

Just check the connection, if the connections are swapped then LVS might identifying tran A & B wrongly.

Or if you have the multiple fingures of A & B, check the connections for all the fingers, error can be there also.

 

[Shohdy]

Hi,

Check if the total number of devices and nets in both circuits is the same. As if not the transistor mapping (between layout and schematic) may be totaly wrong due to wrong connections

Regards,
Shohdy

 

[foreverloves]

thank you!

the number is correct,

in fact, it is a structure as shown in the attached picture, terminal A and B are connected to differient transistors. the two transitors have differient dimension.

in this case, Cadence can not distinguish the two transitors therefore size error occurs

but the problem is: how to solve it ??

 

[truebs]

hi

the porblem might be because of symetrical nature of your circuit. try to put some label on nets or transistor so that it could resolve ambiguities. However this error does not mean that layout or connection is wrong. You can still proceed if only this error is ther in your layout (infact it must be a warning).

 

[renwl]

thank you!

the number is correct,

in fact, it is a structure as shown in the attached picture, terminal A and B are connected to differient transistors. the two transitors have differient dimension.

in this case, Cadence can not distinguish the two transitors therefore size error occurs

but the problem is: how to solve it ??

Is the net name A and B assigned to the same net?[/b]

 

[foreverloves]

hi

the porblem might be because of symetrical nature of your circuit. try to put some label on nets or transistor so that it could resolve ambiguities. However this error does not mean that layout or connection is wrong. You can still proceed if only this error is ther in your layout (infact it must be a warning).

thank you!!

if i put labels on nets, they are put on both nets, so it is possible that Cadence still cannot distinguish them

any other suggestions? thank you

 

[Shohdy]

Hi,

I want to ask if nets A and B are connected to each other as shown in the image above????

Regards,
Shohdy

 

[foreverloves]

Hi,

I want to ask if nets A and B are connected to each other as shown in the image above????

Regards,
Shohdy

yes, they are connected together

but they are with differient dimensions

 

[Shohdy]

can you send the part of netlist that's making the problem????

 

[foreverloves]

hi

the porblem might be because of symetrical nature of your circuit. try to put some label on nets or transistor so that it could resolve ambiguities. However this error does not mean that layout or connection is wrong. You can still proceed if only this error is ther in your layout (infact it must be a warning).

by the way , how to label differient transistors?

Added after 36 seconds:

can you send the part of netlist that's making the problem????

NM4 (net29 net29 gnd N\-sub) nmos_3p3 w=5u l=2.5u....................
NM2 (net29 net29 gnd N\-sub) nmos_3p3 w=10u l=2u ......................

the two transistors NM4 and NM2 have totally the same net connections

 

[sunny153]

Try to match the ROD name/Instance name of the schematic and layout same for A & B. If not, edit the property of the A & B, and match it as per the schematic. The error might go..

 

[Hughes]

Two transistors are connected in parallel. You may add permute rule for parallel mosfets. Then they will be treated as a single device both in layout and in schematic.
If you don't like to combine the parallel devices (since they have different lengths), you may use correspondence points to specify which device in layout should be correspondent to which device in schematic.

 

[safwatonline]

Two transistors are connected in parallel. You may add permute rule for parallel mosfets. Then they will be treated as a single device both in layout and in schematic.
If you don't like to combine the parallel devices (since they have different lengths), you may use correspondence points to specify which device in layout should be correspondent to which device in schematic.

hello Hughes,
can u explain how to do that?
does adding a label in both schematic and layout to one of the transistor will solve this?
thnx alot

 

[isaacnewton]

It will not work.

Try to match the ROD name/Instance name of the schematic and layout same for A & B. If not, edit the property of the A & B, and match it as per the schematic. The error might go..

Added after 2 minutes:

How to ADD PERMUTE RULE for parallel Mosfets?

Two transistors are connected in parallel. You may add permute rule for parallel mosfets. Then they will be treated as a single device both in layout and in schematic.
If you don't like to combine the parallel devices (since they have different lengths), you may use correspondence points to specify which device in layout should be correspondent to which device in schematic.

hello Hughes,
can u explain how to do that?
does adding a label in both schematic and layout to one of the transistor will solve this?
thnx alot

I had same problem before. Adding labels would not work.

 

[isaacnewton]

Terminal A and B are the same point. You can not put two terminals at the same net.

thank you!

the number is correct,

in fact, it is a structure as shown in the attached picture, terminal A and B are connected to differient transistors. the two transitors have differient dimension.

in this case, Cadence can not distinguish the two transitors therefore size error occurs

but the problem is: how to solve it ??