naeim29
Newbie level 5
Hi dear all,
I'm designing a single_stage amplifier,according to figure1 when i try to increase DC-gain of amplifier the phase margin reduces and vice verse.i have some questions if you guys can help me i would be so appreciated;
1-should all transistors go to saturation region?i have tried so much to change all transistors region to saturation but it was not possible!
2-this is a single-stage amplifier in 65nm cmos process,is it possible to get a phase margin around 60 degree and DC-gain around 50dB(open-loop) with a single-stage amplifier?
Best regards
I'm designing a single_stage amplifier,according to figure1 when i try to increase DC-gain of amplifier the phase margin reduces and vice verse.i have some questions if you guys can help me i would be so appreciated;
1-should all transistors go to saturation region?i have tried so much to change all transistors region to saturation but it was not possible!
2-this is a single-stage amplifier in 65nm cmos process,is it possible to get a phase margin around 60 degree and DC-gain around 50dB(open-loop) with a single-stage amplifier?
Best regards
