1) Determine the technology's maximum ion track length.
2) Do the arithmetic to figure out what charge that puts
in the silicon. Assume 100% collection (though it could
be more, if parasitic gain elements are inadequately
suppressed; latchup, even).
3) Put a pulsed current source across whatever PN
junction you are most interested in (leaving the topic
of FDSOI for another decade). Scale its width to the
likely technology timescale (hundred pS for low voltage
logic, nS for medium voltage linears, tens of nS for deep
junction power devices. Scale the amplitude such that
delivered charge is as-calculated in 2). Make the delay
time a user variable (e.g. t_seu) so you can impose the
error stimulus at a time of your choosing (or march it
across a cycle, as sensitivities vary with state).
4) Now, do this for every element in the circuit, each of
its relevant terminal-pair combinations, each different
circuit state.
5) Now inspect for what showed a reaction, and move on
to "why?" and then "whaddyagonnadoaboudit?".
6) Oh, you thought you got them all? Well, check again.
Sometimes the "fix" is just another "victim".
When you want to design unupsettability in a serious
way, you will want to develop some personal tools
(Cadence has nothing for it; Silvaco's native capability
is just clunky). I recommend you hire a consultant
https://www.google.com/search?q="single event transient"+simulation