single ended clock connected to the N-side differential pin

[hg527]

Hi,everyone:

I use Virtex5 and ISE10.1. I connect one chip’s single ended clock to the N-side of clock capable pins of Virtex5 FPGA by accident on my PCB board. But Xilinx’s manual demands ：“1）Do not connect a single ended clock to the N-side of the differential clock pair of pins, for example IO_L3N_GC_3. 2）Do not connect a single-ended clock to the N-side of clock capable pins, for example, IO_L8N_CC_11”. It’s really a tragedy.

However,I use ISE10.1 to place and route my synthesized results and there is no errors reported. Indeed, floorplan show errors as above mentioned.

The world is relative. Clock signal and other signals also are relative. Does it mean some primitives, such as BUFG, PLL_ADV, DCM_ADV, cannot be placed or routed to FPGA chip pad?

My question is :

1) What is the result if I connect a single ended clock tothe N-side of clock capable pins?

2) If it is dangerous or can not implement, How can I do? After all，it is a hardware ‘hurt’.

3) What’s the difference between P-side and N-side? Do we have the common sense that P-side is ‘rich’while N-side is ‘poor’? What is the architecture of the IOB?

Do anyone have advice？ Who can explain？ Thanks forever.

 

[TA37]

Not sure about the V5, but earlier versions did give you a little slack. For instance, non clk pins will use internal routing to get to the BUFG rather than the associated pad's direct connection. For slower clocks this doesn't matter. I'm guessing the N-pads are the same way: suboptimal performance in terms of skew, etc. but should still 'work.'

And if you've already built hardware, couldn't hurt to just try it.

 

[hg527]

Re: single ended clock connected to the N-side differential

Dear TA37:
Thank you for your replay. I think maybe you are right. I will try it and hope it will work.
Xinlin’s manual says:
“Each differential global clock pin pair can connect to either a differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side of the pin pair must be used because a direct connection only exists on this pin. If a single-ended clock is connected to the P-side of a differential pin pair, then the N-side cannot be used as another single-ended clock pin. However, it can be used as a user I/O.”
But I do not understanding what ‘a direct connection’ is. I work hard to find differences between the P-pad and N-pad.
Thanks!
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