Sine wave- missing samples

[Careline]

Hello...I am very new to VHDL.. I have generated sine wave in VHDL.. But the problem is that some samples are missing in the output and so the wave is distorting... In PSK,FSK programs the same problem is occurring.. What should i do?? I tried matching the frequency but still the result is same..:roll: Guide me..Thank you...

 

[TrickyDicky]

Post the code - maybe we can help.

 

[Careline]

Here is the code

architecture Behavioral of fsk is
signal i : integer := 0;
signal k : integer := 0;
signal b : std_logic := '0';
signal o_dummy : integer := 0;
signal temp : std_logic := '1';
signal j : integer range 0 to 249;
signal c : integer := 0;
signal c1 : integer := 0;
signal c2 : integer := 0;
type array_int is array (0 to 249) of integer;
type array_in is array (0 to 124) of integer;
signal carrier1 : array_int := (512,524,537,550,563,576,588,601,614,626,639,651,663,676,688,700,711,723,735,746,758,769,
780,791,801,812,822,832,842,852,861,871,880,888,897,905,913,921,929,936,943,950,956,962,968,974,979,984,989,993,997,1001,1005,
1008,1011,1013,1016,1018,1019,1021,1021,1022,1022,1022,1022,1021,1021,1019,1018,1016,1013,1011,1008,1005,1001,997,993,989,
984,979,974,968,962,956,950,943,936,929,921,913,905,897,888,880,871,861,852,842,832,822,812,801,791,780,769,758,746,735,
723,711,700,688,676,663,651,639,626,614,601,588,576,563,550,537,524,512,500,487,474,461,448,436,423,410,398,385,373,361,348
,336,324,313,301,289,278,266,255,244,233,223,212,202,192,182,172,163,153,144,136,127,119,111,103,95,88,81,74,68,62,56,50,
45,40,35,31,27,23,19,16,13,11,8,6,5,3,3,2,2,2,2,3,3,5,6,8,11,13,16,19,23,27,31,35,40,45,50,56,62,68,74,81,88,95,103,111,119,
127,136,144,153,163,172,182,192,202,212,223,233,244,255,266,278,289,301,313,324,336,348,361,373,385,398,410,423,436,448,
461,474,487,500);
signal carrier2 : array_in := (512,537,563,588,614,639,663,688,711,735,758,780,801,822,842,861,880,897,913,929,943,
956,968,979,989,997,1005,1011,1016,1019,1021,1022,1022,1021,1018,1013,1008,1001,993,984,974,962,950,936,921,905,888
,871,852,832,812,791,769,746,723,700,676,651,626,601,576,550,524,500,474,448,423,398,373,348,324,301,278,255,233,212
,192,172,153,136,119,103,88,74,62,50,40,31,23,16,11,6,3,2,2,3,5,8,13,19,27,35,45,56,68,81,95,111,127,144,163,182,202,223,
244,266,289,313,336,361,385,410,436,461,487);
begin
o <= o_dummy;
process(clk)
begin
if rising_edge(clk) then
i <= i + 1;
if i < 2000 then
b <= '1';
elsif i < 4000 then
b <= '0';
else
i <= 0;
end if;
if j = 249 then
j <= 0;
else
j <= j + 1;
c1 <= carrier1(j);
end if;
if k = 124 then
k <= 0;
else
k <= k + 1;
c2 <= carrier2(k);
end if;
if b = '0' then
o_dummy <=c1;
else
o_dummy <= c2;
end if;
end if;
end process;
end Behavioral;

 

[std_match]

You are skipping one sample value when j is 249 and when k is 124.
When you do the wrapping to zero, the previous sample value is used again.
You should do the assignments to c1 and c2 every clock cycle.

 

[Careline]

Yes.. The sample values are not starting at the same time the counter is starting.. But I am assigning c1 and c2 every clock cycle right?? Where am I wrong??

 

[FvM]

But I am assigning c1 and c2 every clock cycle right??

Nop. Place the "end if" statements before the "c1 <=" and "c2 <=" assignments.

 

[Careline]

Yes i placed them as you said, but still the result is same. After many cycles the distortion in the signal is making it look like a PSK signal

 

[std_match]

The output will alternate between c1 and c2.
The output will come from c2 for 2000 clock cycles and then from c1 for 2001 clock cycles.
Is that what you see?

 

[Careline]

Yes.. The output is from c1 for 2001 cycles.. But the count for 2001th cycle is 0. And the next cycle is starting from 1.

 

[Careline]

Does anyone have idea to solve this??? This problem is repeating if i combine waveforms like pulse,ramp,square in a single output.

 

[FvM]

I think the problem is about understanding the behaviour of registered signals in VHDL and design your code respectively.

As a first step, sketch the intended signal timing in a waveform or a list. Watching the actual behaviour in a functional simulation will also help to figure out the problem.