# Presudo random noise to sine wave (VDHL, ModelSIM)

##### Newbie
Hey. I am new to VHDL programming topic. Faced with an overwhelming task. Objective: to simulate a noise generator for a signal. I have searched and read a lot of articles and posts on the forum. Found the following code. The problem is that when I execute it, I get the result shown in the screenshot below. Can you help me get it up and running correctly? The author of the post has a screenshot where the code is working correctly. But communication with him has been lost.

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.

entity sine_wave is
generic ( width : integer :=  4 );
port (clk :in  std_logic;
random_num : out std_logic_vector (width-1 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end sine_wave;

architecture Behavioral of sine_wave is
signal data_out1,rand_temp1,noisy_signal : integer;
signal noisy_signal1 : STD_LOGIC_VECTOR(7 downto 0);
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0);
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
--to check the rising edge of the clock signal
if(rising_edge(clk)) then

temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;

--data_out <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
data_out <= sine(i);
data_out1<=to_integer(unsigned(sine(i)));
random_num <= rand_temp;
rand_temp1<=to_integer(unsigned(rand_temp));
noisy_signal<=data_out1+rand_temp1;
noisy_signal1<= std_logic_vector(to_signed(noisy_signal,8));
end process;

end Behavioral;

#### barry

3) What do you think is wrong? I see a noisy sine wave, isn’t that what you want? Or is that right hand waveform something else? I’m guessing maybe that’s somebody else’s waveform. If you want a clear answer, post a clear question.
4) if the code you show is copied, as you say, then it’s doing exaptly what it’s supposed to.
5) but I think your biggest problem is that you have no clock: that red line at the top of the chart.

##### Newbie
3) What do you think is wrong? I see a noisy sine wave, isn’t that what you want? Or is that right hand waveform something else? I’m guessing maybe that’s somebody else’s waveform. If you want a clear answer, post a clear question.
4) if the code you show is copied, as you say, then it’s doing exaptly what it’s supposed to.
5) but I think your biggest problem is that you have no clock: that red line at the top of the chart.
Thanks for your reply. Right hand waveform not my. I have never worked with modelsim software, so I don’t know how to add and control the clock.

#### barry

I think you need to learn about test benches; that's where you can generate your clock. But you can also do it directly in Modelsim. Right click on the clk signal in the waveform, click "clock..." and define your clock parameters.

##### Super Moderator
Staff member
or type the following in the Tcl console:
Code:
force clock 0, 1 5 ns -r 10 ns
change the 5 ns and 10 ns to match the actual period of the clock to be used.

As barry suggests you are better off learning how to write a testbench.