sine wave does not generate output when there is another module in the simulator

[ruwan2]

Hi,

I use SMASH to learn verilog-AMS. I find that when I instantiate a sine wave generator only in SMASH, it can generate sine wave as I expect. When I add another module, no matter digital or analog, the sine wave output has only very small peak value noise (The names of sine module and amp module are different. Thus they are not shorted?).

Below is the head amp_out.pat file:

.lib "amp_out.vams"
.lib "sine_source.vams"
*.ELABORATE work.amp
.ELABORATE work.sinVarFreq
.Trace Tran src Min=-1.0000000e+00 Max=3.0000000e+00

xsine src src_n sinVarFreq

.Eps 1u 100m 100n
.H 1fs 1fs 1ns 125m 2
.Tran 1ns 100ns 0s noise=yes noisestep=1ns traceBreak=yes compress=no compressCoeff=1 compressTolX=0 compressTolY=1u powerup=no timeup=0s predict=no
.Option Tuning=Swift Swift=1m
.Method TRAP lte=no
.PRINT TRAN IN(M)
.LPRINT testbench.b testbench.buf0.in

Here are sine and amp modules:

`include "disciplines.vams"
`include "constants.vams"

module sinVarFreq(p, n);

inout p, n;
electrical p, n;

parameter real freq = 100.0e2;
parameter real coeff = 1.0e-3;
real tempr;

analog begin
V(p,n) <+ sin(`M_TWO_PI * freq * $abstime * 8e2);
end
endmodule
..............

`include "disciplines.vams"

module amp(out, in);
inout out, in;
electrical out, in;
parameter real Gain = 1, Rin = 1, Cin = 1, Rout = 1, Lout = 1;

analog begin
// gain of amplifier
V(out) <+ Gain*V(in);
// model input admittance
I(in) <+ V(in)/Rin;
I(in) <+ Cin*ddt(V(in));
// model output impedance
V(out) <+ Rout*I(out);
V(out) <+ Lout*ddt(I(out));
end
endmodule

When I comment out

*.ELABORATE work.amp

it will have no sine wave in transient wave window.





I do not see restrictions on AMS LRM or SMASH reference book. What is wrong with my usage?


Thanks,