Simultaneous conduction - PMOS and NMOS

[AMSA84]

Hi guys, I've a problem here with simultaneous conduction in a buck converter. Cadence. C=10nH, L=20nH

As you can see on the picture below, the converter has a simultaneous conduction when the VDS and VSD cross each other. I've tried different ways to setup the vpulse source (delay, pulse width, etc) but I didn't got rid of that current spike in the PMOS (ligh blue).

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Does anyone can give me a tip on how can I fix this problem? The current spike on the PMOS drain? I know that is related to dead-time but I can figure it out on how to implement/configure the vpulse in order to minimize the spike.

Regards. Thanks in advance.

 

[cl10greg]

What MOSFETs are you using (or at least what parameters)? Have you tried to add a pull up and pull down resistor on the PMOS and NMOS gates? How much of a delay did you add between the two signals? What PWM pulses are you applying to the gates? How much current are provided by the PWM signal?

There could be multiple issues that is why I am asking.
1.) If there is not a sufficent gate deactivation path, it will take time for the gate to discharge and to turn on and off (hints the pull up/down resistors)
2.) The PWM signal doesn't provide sufficent current for fast turn on times (it takes too long to charge the gate which increases the on times)
3.) The signal isn't delayed enough to account for the rise and fall times of the MOSFETs
4.) The voltage is too low where the MOSFET is close to the linear region

 

[SIDDHARTHA HAZRA]

The VDS and VSD signals are fine .... they will cross each other at the same time ... as the drain node is common to both NMOS & PMOS .... that does not mean both are conducting ... can you please check and plot the drain current of the NMOS .... In fact it would be great if you can plot the currents through inductor, NMOS drain, PMOS drain, V14 & V13 ....

 

[AMSA84]

Hi and thanks for the reply.

What MOSFETs are you using (or at least what parameters)?

PMOS W=6000u and NMOS W=2000u @ 130nm tech.

Have you tried to add a pull up and pull down resistor on the PMOS and NMOS gates?

Nop, but I tried a series resistance in the gate because I read somewhere that we need to know the current that we'll supply to the gates according to the CGS and CGD of the MOSFET taking at same time into account the rise and fall times. So I tried by trial and error to tune those resistances in the gate in order to reduce the current and I got some improvements but not much. At same time I've enlarged the dead-time (the space between the PMOS and NMOS gate signals and now I am having a maximum current around 600mA between the terminals of the PMOS. The shape of the current signal is not so likely as we see on the books.

How much of a delay did you add between the two signals?

0.4ns

What PWM pulses are you applying to the gates?
I am simulating with Ideal Pulse generators.

How much current are provided by the PWM signal?


There could be multiple issues that is why I am asking.

1.) If there is not a sufficent gate deactivation path, it will take time for the gate to discharge and to turn on and off (hints the pull up/down resistors)

2.) The PWM signal doesn't provide sufficent current for fast turn on times (it takes too long to charge the gate which increases the on times)

3.) The signal isn't delayed enough to account for the rise and fall times of the MOSFETs

4.) The voltage is too low where the MOSFET is close to the linear region

 

[dick_freebird]

You will never entirely eliminate drain current spikes, the
Cdg/Cds/Cdb are always going to have some displacement
current. If Vgs=0 (which the first plot purports) the drain
current pulses should be minimum width and amplitude. I
suggest applying a risetime-realistic drain step voltage to
a solo FET with Vgs=0, and take the current you get as a
baseline reference - then your goal would be for the
integral of ID(t)dt in the real circuit to be of the same
order (maybe cut yourself 10-20% worth of slack). You
have to know when to quit trying to fight physics. That
wants you to know what's physics and what's design
driven.

 

[AMSA84]

Hi freebird and thanks for your reply.

You are right.

What rise and fall time would you recommend for a period of T=3.333ns (and a width of 1.212121ns for one of the signals that I am applying to the PMOS)? I am using a 100ps (that is 0.1ns). Isn't that value realistic enough?

By the way, what do you think on using some gate resistors in order to reduce the current spikes at the gate? What current should I expect for the gate? I ploted the current entering on the gate of the PMOS and I notice that in there I am having some spikes in the order of 400mA.

Regards.

EDIT: freebird, could you explain again but in another words this:

If Vgs=0 (which the first plot purports) the drain current pulses should be minimum width and amplitude. I suggest applying a risetime-realistic drain step voltage to a solo FET with Vgs=0, and take the current you get as a baseline reference - then your goal would be for the integral of ID(t)dt in the real circuit to be of the same order (maybe cut yourself 10-20% worth of slack).

 

[AMSA84]

By the way, can someone give me a link where I can rad about PMOS gate driver? I am a bit confused with the PMOS gate driver.