I made a filter with simulink and used one of its tools to create vhdl code out of it. I implemented it on an FPGA and it gives me reasonable output except that the frequencies that it pass are not the frequency I designed it to pass. When testing in matlab, a FFT of the output from the filter gives a single peak at 82Hz, but the filter on the board passes 56Hz as well at 170Hz. Any idea what would cause this? Thanks for the help.
r u checking your output using hardware co-simulation in loop??
Can you tell me more about input signal BW, BFP characteristcs, sampling frequency etc.,
hi !
can u tell me how to implement simulink based design in FPGA kit ...
please i have designed a receiver i need to implement in FPGA kit.. please help me