Simulink and Cadence Virtuoso Cosimulation.

Hello guys,
I have implemented a PFD and Charge Pump and I wanted to do a simulation for them as part of a PLL.

without the need to perform verilogA components in cadence, I understood there is a way to take a complete PLL design in Simulink and replace some components with transistor level components from virtuoso.

here is a link that demonstrates the idea:
https://www.youtube.com/watch?v=L8g7Hq0peO8

for our case we want to replace Ideal PFD and Charge Pump in Simulink with transistor level circuits we built in vrituoso.

we found the documentation files for the AMS designer, but for some reason when we try to make the Simulink and Virtuoso talk to each other it seems that when we open the AMS designer some component looks to be unidentified and others are locked.



I'm using : IC6.1.7-64b.500.15 virtuoso version.

any one with experience with the AMS Designer tool can help with this?
I tried to reach cadence for customer support in Israel but the one person that can help is on vacation.
I'm open for any other ways to find a solution/help for this issue.

thanks,
Firas