Simulation vs Verification ?

[asfliy]

simulation vs verification

Can anybody explain what's the difference between simulation and verification?
Thanks!

 

[shiv_emf]

test vs verification


applying values to design under verification is stimulus and this process is called simulation.

Verification is to simulate design n check for its functional correctness

for more information ! refer Janick
Thanks

 

[amihomo]

Hi,
Could you please tell me what is the necessity for creation of verification languages like SystemVerilog , and essentially what is the difference between HDL languages (like VHDL and Verilog) and Verification languages?

regards

 

[ljxpjpjljx]

simulation and verification are totally 2 different thing! Simulation means you can use tools to simulate the DUT actural thread! and the verification means you can verify the DUT with different method!

 

[amihomo]

I mean while we can use VHDL to verify the functional behavior of our design , why create a new language for verification?

 

[ashiram]

Simulation means debugging functional errors in in the DUT.
Verification means Creating test bench and writing test cases . checking DUT functionality after running testcases.

 

[Vishwajeet]

Simulation is to apply the stimulus to the design. It can be done through applying input and checking the output. And ofcourse verification is also a part of simulation. I mean the verification is done by means of simulation . And to your other query, abt HVL - systemverilog, Its just to make the verification engineer's life easy. If you consider highly complicated designs (SOC's) you need more sophisticated verification environment (Mainly Test bench with some intelligence in it) and ofcourse lot of time. And SystemVerilog gives many constructs by which we can construct very sophisticated TB. And as its Object Oriented, with methodologies like OVM, can be easily inherit their class and build our TB in no time. And more over its reusable. I hope this will make your views clear with respect to simulation, verification and HVL like systemverilog.

Regards,
Vishwajeet B

 

[shashank_s_82]

Simulation & verification both uses differential equations to get the response of system by applying i/p test stimulus

In VLSI Simulations are of type arhitectural, behavioural, gate-level, switch level, transistor level etc. in these simulation we try to get the systems response for desired i/p pattern
tools: Model sim-simulator, HSPICE for tran level sim, PT for STA etc.

In verification we normaly verify what we've ctreated eg are formal verification, functional verification
tools Conformal, formality etc.

 

[rtl2gates_user]

Traditional difference between simulation and functional verification is that simulation is running your design with a set of vectors (analog or digital) and functional verification is a superset of simulation where you interpret the results of your simulation and draw a conclusion for your design spec.

As a side note i am using this oppurtunity to promote www.rtl2gates.com website.

Thanks