Simulation time-advance cycle

Status
Not open for further replies.
I

ijy

Newbie
Joined
Oct 1, 2022
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
21
I am taking a course on digital design as part of my undergrad, and I am stuck on a homework problem. One part of the problem asks "explain how one should choose the simulation step size, if one does not just use a default value provided by the simulator."

I cannot find any mention of this in my digital design textbooks, the VHDL-2008 standard, or any search engine results. Can anyone tell me how the minimum simulation step size is determined and if a designer can have control over this value?

I read on a separate thread that the simulation can be either "event" simulation or "cycle" simulation. I am assuming that cycle simulation means the simulation step size is equal to 1/2 the clock rate. Would this then be the smallest useful step size?
 
Last edited:

Sort by date Sort by votes
The time step should be brief enough so that changes are slight from one simulation frame to the next.

* To choose a reasonable length of time step, make it so between 100 and 10,000 of them fit into a frequency source you designate in your schematic.

* Certain events happen so fast that you need to choose a shorter time step in order to have detailed action show up in the simulation.

* Sometimes your scope trace is a lissajous figure. If the time step is too long then it causes a curve to appear to be drawn with straight lines. In that case try a shorter time step.
 

Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…