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| --------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
USE work.edge_package.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY camera IS
GENERIC( fi_n: STRING :="hexi.dat" ; -- Input hex file name
tclk: TIME:= 100ns -- Clock speed
);
END camera;
ARCHITECTURE behavior OF camera IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dwt
PORT(
clk : IN STD_LOGIC;
vid_in : IN STD_LOGIC_VECTOR(7 downto 0);
hor_sync: IN STD_LOGIC;
vert_sync: IN STD_LOGIC;
val_flag : IN BIT;
vid_out : OUT STD_LOGIC_VECTOR(7 downto 0);
v_out: OUT STD_LOGIC;
h_out: OUT STD_LOGIC;
val_out: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT moniter
PORT(
clk_i : IN STD_LOGIC;
vid : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
v_in : IN STD_LOGIC;
h_in: IN STD_LOGIC;
val_in: IN STD_LOGIC;
sts: OUT STD_LOGIC
);
END COMPONENT;
--Inputs
FILE image: TEXT OPEN read_mode IS fi_n;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL vid_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL hor_sync: STD_LOGIC:='0';
SIGNAL vert_sync: STD_LOGIC:='0';
SIGNAL val_flag : BIT := '0'; --Data Validation flag
SIGNAL vid_t: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
SIGNAL hor_t:STD_LOGIC:='0';
SIGNAL ver_t:STD_LOGIC:='0';
SIGNAL val_t:STD_LOGIC:='0';
SIGNAL finish:STD_LOGIC:='0';
--Outputs
SIGNAL vid_out: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dwt PORT MAP (
clk => clk,
vid_in => vid_in,
hor_sync=>hor_sync,
vert_sync=>vert_sync,
val_flag => val_flag,
vid_out => vid_t,
v_out=>ver_t,
h_out=>hor_t,
val_out=>val_t
);
--Instantiate display device
uut1: moniter PORT MAP(
clk_i => clk,
vid => vid_t,
v_in => ver_t,
h_in => hor_t,
val_in => val_t,
sts => finish
);
-- Stimulus process
stim_proc: PROCESS
VARIABLE chr: CHARACTER;
VARIABLE buf: LINE;
VARIABLE good: BOOLEAN:=FALSE;
VARIABLE vid_tmp: STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE tmp: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF NOT(ENDFILE(IMAGE)) THEN
READLINE(image,buf); ---Read Hex image file to buffer
FOR i IN buf'RANGE LOOP
READ(buf,chr,good); ---Character read from the buffer
IF (good=FALSE) THEN
EXIT;
END IF;
IF(chr=',' ) THEN
val_flag<='0';
hor_sync<='1';
vert_sync<='0';
ELSIF(chr='*') THEN
val_flag<='0';
vert_sync<='1';
hor_sync<='0';
ELSE
hor_sync<='0';
vert_sync<='0';
val_flag<='1';
stdlogic_conv(chr,tmp); --Procedure to convert hexadecimal string to std_logic_vector
vid_tmp(7 DOWNTO 4):=tmp;
READ(buf,chr,good);
IF (good=TRUE) THEN
stdlogic_conv(chr,tmp);
vid_tmp(3 DOWNTO 0):=tmp;
END IF;
END IF;
vid_in<=vid_tmp;
WAIT UNTIL RISING_EDGE(clk);
END LOOP;
ELSIF (vert_sync='1') THEN
--If the output file is written, abort the simulation
--IF(finish='1') THEN
-- ASSERT (FALSE) REPORT "Simulation failed!" SEVERITY FAILURE;
--END IF;
WAIT UNTIL RISING_EDGE(clk);
END IF ;
END PROCESS stim_proc;
ASSERT (finish/='1') REPORT "One Frame Completed!" SEVERITY WARNING;
clk <= NOT clk AFTER tclk; -- Clock generation
END ; |