The error you are seeing is the systematic offset. Surely transistors in the same mirror have different Vds. This makes the output current to be different from the input current. You should make, by using regulated mirrors, both Vds to be the same.
Additionally, do not forget to make Monte Carlo simulations as the mismatch between transistors also contributes to the total error. Even MC simulations from your schematic will show you that. No need to go to post-layout sims to see the effect. Post-layout sims will show you parasitic contributions and path mismatch effects, which add to the previous errors.