There is always the possibility of a PDK or model error, I
suppose. What about taking the two believed-identical
flavors and running them side by side in a DC testbench,
looking at ID vs VG, ID vs VD curve families?
Maybe the netlister swaps W for L, or something silly.
However I wouldn't discount the possibility that the
problem lies upstream, and some small difference in
transistor attributes has put you on the wrong side
of some other bias setpoint like the diff pair throwing
too much current for the sink sizing to handle, etc.
There are a lot of externalities to that block, any of
which could bug it. Maybe you want a few less bias
loops to begin with, or pin the ones that you think
you know proper points for.