Simulation problem on the effect of decoupling capacitor

[taofeng]

Dear,

I am using the attached schematic to simulate the effect of Decoupling capacitor (someone may call it bypass , anyway it does not really matter) on the reduction of the power supply current transient as probably known to all of you guys.
However, no matter how I change the value of Decap (C2 in the schematic), the Current see from the power supply (V1) and the Current flowing through the inverter (Pmos transistor) remain exactly the same, which means that the C2 does not supply the transient . It seems really strange, I do not know what is wrong with this setup ?
Hope someone can give me some hint ! thanks

Jeffrey

 

[safwatonline]

the cap is parallel to ideal source !!

 

[taofeng]

hi safwatonline,

What should I do , could you make it clear ?

regards,

jeffrey

 

[jfyan]

hi safwatonline,

What should I do , could you make it clear ?

regards,

jeffrey

hi

try to find this paper:
"parasitic resistance in an mos transistor used as on-chip decoupling capacitance".

the voltage source model should be constructed more realistically.

jeff

 

[safwatonline]

Hello,
u need to add a more real model, like adding bond wire model and on chip parasitic routing inductors and resistors