simulation of clock domain crossing CDC path

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tariq786

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Hi,

I have a question about simulation of a design having multiple clock domains with CDC paths (one or more) between the clock domains.

How do you verify these paths by simulation? I mean can you verify by simulation that CDC is working properly? If so, how will you report coverage?

Any hints, pointers, links

Please give easy to understand and thorough explanation like yadavvlsi :grin:
 

Mentor provides a tool call questa CDC formal, that read the modelsim/questa data base and analyze the code to check if the minimum double flops are present to exchange data from one clock domain to another clock domain.
By simulation, it is not really easy to check this. Random clock frequency could help, with huge number of simulation.
"paper" analysis to find/detect the worst clock ratio....
 
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