I have used the Xilinx Design Manager to generate a vhdl file and used Modelsim to simulate the gate level design
Select Design -> Options -> Simulation -> Generic VHDL
Then Select Edit Options -> Simulation Data Options -> VHDL. Check Correlate Simulation Data to Input Design
Simulation Netlist name = name of VHDL file to be generated (e.g. timesim.vhd)
Now you have a vhdl file you also need the vital files which can be found in the xilinxvhdlsrcsimprims directory. Make a library simprim in modelsim (vlib simprim) and compile simprim_Vcomponent.vhd, simprim_VITAL.vhd and simprim_Vpackage.vhd to this library. Now you can simulate the gate level design.