Simulation of circuit with Xilinx Foundation 4.1

[OvErFlO]

modelsim 5.5se

How can I simulation circuit with Xilinx Foundation 4.1? (there isn't any package)
I remember that in Fondation 2.1 it exists... How can I do ?

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Please don't reply unless you have useful information to add on this post. Thanks

 

[knavekid]

You need something like Model*Sim to go with it. It is included with Foun*dation I S E 3.1i and 4.1, but it comes on a separate CD. A 4.1 ISO of the CD wouldn't have it. Try to find a Mode*lSim ISO and go from there.

 

[OvErFlO]

I have mod*els*im 5.5 SE and PE but this not have chip xi*li*nx.... Can you help me... Tnx...
I know a version XE but it's ippossible fint it...

 

[OvErFlO]

I have mod*els*im 5.5 SE and PE but this not have chip xi*li*nx.... Can you help me... Tnx...
I know a version XE but it's impossible fint it...

 

[Froed]

use any Modelsim Version you have.

to simulate the Gate-level (i.e. after Place and Route )

write out a verilog netlist.

Then compile the used xilinx-Technology in a library of your choice.

Load the design with this Library and then you can simulate it

 

[ElekPK]

I have used the Xilinx Design Manager to generate a vhdl file and used Modelsim to simulate the gate level design

Select Design -> Options -> Simulation -> Generic VHDL
Then Select Edit Options -> Simulation Data Options -> VHDL. Check Correlate Simulation Data to Input Design
Simulation Netlist name = name of VHDL file to be generated (e.g. timesim.vhd)
Now you have a vhdl file you also need the vital files which can be found in the xilinxvhdlsrcsimprims directory. Make a library simprim in modelsim (vlib simprim) and compile simprim_Vcomponent.vhd, simprim_VITAL.vhd and simprim_Vpackage.vhd to this library. Now you can simulate the gate level design.