There are issues with the no_timing_check depending on how the std cell library gate level verilog is described. You might make the setup/hold warning messages disappear, but the Xs are still there. I know I have had that issue before, it's worth checking.
What I meant about fake delays is that you can try to purposefully make your RTL simulation work on the opposite edge as the gate level simulation, this should prevent all the hold issues. Then you are only left with setup.