sdmotewar
Newbie level 6
can anybody help me !
i m doing dsp processor design in vhdl
for designing alu, for signed operation, i m getting simulation error 29, saying
"Default port map for entity alu_L to component
alu_L connects std_ulogic type local port carry_out of the component to BIT
type port of the entity."
what is the problem
i m doing dsp processor design in vhdl
for designing alu, for signed operation, i m getting simulation error 29, saying
"Default port map for entity alu_L to component
alu_L connects std_ulogic type local port carry_out of the component to BIT
type port of the entity."
what is the problem