simulation error 29 in vhdl(ise)

can anybody help me !
i m doing dsp processor design in vhdl
for designing alu, for signed operation, i m getting simulation error 29, saying
"Default port map for entity alu_L to component
alu_L connects std_ulogic type local port carry_out of the component to BIT
type port of the entity."


what is the problem

Hi,

You can not connect ports of different types to each other without using a conversion function.

From the error message, you connect a std_ulogic port to a bit port. You cannot do that. You need to use the conversion function to_bit or to_stdulogic to connect the ports to each other. Both function are in the std_logic_1164 package.

Devas

thanks devas,
actually i declared i/ps as either unsigned, or bit type in a package, but while simulating using test bench vhdl file or by test bench waveform this error of port map is coming, i have tried in my test bench vhdl file by changing i/p or by using to_unsigned but its not working.

Hi,

When you post your code we can look into it what is causing this issue.

Devas

files r attached as follow

Hi,

I do not see any attachement.

Devas

code for signed alu unit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
use work.dsp_pac.all;
use work.alu_types.all;



entity alu_L is
port(s1: in DM_data; -- dm_data is unsigned(15 downto 0);
s2: in DM_data;
result : out DM_data;
func : in alu_func;
zero, negative,carry_out: out bit);
end entity alu_L;

architecture Behavioral of alu_L is
begin

alu_op: process(s1,s2,func) is
procedure add ( L,R : in DM_data;
result: out DM_data;
carry_out : out bit;
carry_in : in bit;
signed : in boolean) is
variable carry : bit := carry_in;
variable carry_prev : bit;

begin

for index in result'reverse_range loop
carry_prev := carry;
result(index) := L(index) xor R(index) xor carry;
carry := (L(index) and R(index)) or (carry and (L(index) xor R(index)));

end loop;
if signed then
carry_out:= carry xor carry_prev;
else
carry_out := carry;
end if;
end procedure add;

variable temp_result : DM_data;
variable temp_carry: bit;
begin
temp_carry := '0';
case func is

when alu_add =>

add(s1, s2, temp_result, temp_carry,
carry_in => '0', signed =>true);

when alu_addc =>
add(s1, s2, temp_result, temp_carry,
carry_in => '1', signed => true);

when alu_sub =>
add(s1, not s2, temp_result, temp_carry,
carry_in => '0', signed => true);

when alu_subc =>
add(s1,not s2, temp_result, temp_carry,
carry_in => '1', signed => true);


when others =>
report "illegal function code" severity error;
temp_result := x"0000";
end case;

result <= temp_result;
zero <= bit'val (boolean'pos(temp_result=X"0000")) ;
negative <=temp_result(15);
carry_out<= temp_carry;
end process alu_op;



end architecture Behavioral;

Hi,

Oke this is one part of your design, but your original error was in a port map, so you have also a file in which alu_L has been instantiated (your testbench file?). And from another post you say that you have a component declaration in a package.

To have a look I need:
- the entity alu_L (I have now)
- the component declaration of alu_L if available
- the instantiation of alu_L (and also the types of the ports it is connected to)
- the package declaration of DM_data and alu_func

When you do not want to post all your code, you may strip your design until you have only that part that creates the error, so something of a file that has a component declaration of alu_L and an instantiation of alu_L.

Devas

thanks

1.- entity alu_l hv given
2.- component alu_l not declared but in test bench it comes as
ARCHITECTURE behavior OF alu1_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu_L
PORT(
s1 : IN std_logic_vector(15 downto 0);
s2 : IN std_logic_vector(15 downto 0);
func : IN std_logic_vector(5 downto 0);
result : OUT std_logic_vector(15 downto 0);
zero : OUT std_logic;
negative : OUT std_logic;
carry_out : OUT std_logic
);
END COMPONENT;
3. - presentaly alu is not connected , i m simualting only alu entity
4.- package consists dm_data as unsigned(15 downto 0);

Hi,

Your component declaration should be an exact copy of the entity declaration. In your case it is not. In your component declaration you use std_logic/std_logic_vector while your entity uses bit/unsigned. These types are not the same.

1. Change component declaration to match entity
2. When you want to use the instantiation of entity alu_L and to connect the ports of this entity to signals of different types you must use conversion functions.

Devas

helo

in my entity declaration i used , if i used std_logic_vector it gives errors for index operation, and if i chane component in text bench then also it shows component mapping error as unsigned port mapped to unsigned

Hi,

Yes, because you can NOT connect std_logic_vector to unsigned without using a conversion function. So,

1. Component DECLARATION: should be the same as entity DECLARATION (unsigned)
2. Component INSTANTIATION: use conversion functions in the port map to convert unsigned to std_logic_vector and v.v. (but better for you would be to use unsigned everywhere in your design)

Devas

thanks for help
but can u give ur mail id, i wil send my files
here some problem with attachment.

Hi,

I have send you a pm.

Devas