Jaffry
Member level 1
Dear all,
I am relatively new in FPGA practical design, earlier I had expereince of simulation designs for verilog and VHDL
models.
This time I am working on a practical project. For that I have completed my simulation phase and the results are good to be implemented.
Now the implementation phase have arrived and I need guidance in this regard, I have done homework regarding my next steps. but any help would be beneficial and would increase my speed since I have to complete this (and finished and delivered) within 1 1/2 month from now...
My next steps should be (Please provide with a good thorough link or materail as well if can)
1) Static Timing Analysis (Dynamic Timinig analysis- if required)
This is the most time consuming phase I think will be for me. Since I could not understand what clock frequency is best for my design. I have read about timing constraints, but how to find the parameters using reports is difficult. I can also share details what difficulties I find....
2) Place and Route : This Xilinx ISE will do itself based on .UCF file and STA
3) download into fpga: using iMpact. I have idea of this as I have done this several time with small projects like counter, d flipflops etc.
Note : I am using xilinx V6 Fpga board + Xilinx ISE software and Language is Verilog
Best Regards,
Jaffry
I am relatively new in FPGA practical design, earlier I had expereince of simulation designs for verilog and VHDL
models.
This time I am working on a practical project. For that I have completed my simulation phase and the results are good to be implemented.
Now the implementation phase have arrived and I need guidance in this regard, I have done homework regarding my next steps. but any help would be beneficial and would increase my speed since I have to complete this (and finished and delivered) within 1 1/2 month from now...
My next steps should be (Please provide with a good thorough link or materail as well if can)
1) Static Timing Analysis (Dynamic Timinig analysis- if required)
This is the most time consuming phase I think will be for me. Since I could not understand what clock frequency is best for my design. I have read about timing constraints, but how to find the parameters using reports is difficult. I can also share details what difficulties I find....
2) Place and Route : This Xilinx ISE will do itself based on .UCF file and STA
3) download into fpga: using iMpact. I have idea of this as I have done this several time with small projects like counter, d flipflops etc.
Note : I am using xilinx V6 Fpga board + Xilinx ISE software and Language is Verilog
Best Regards,
Jaffry