Thank you all for your reply.
Yes I synthesized the design. It is synthesized (of-course I had to fix some problems
) Any ways. So I am getting some warnings (some of which are related to IP cores I guess, i.e. Divider core )
So should I ignore these warnings.
Also I tried one more thing...
A single clock domain is usually desired. Crossing clock domains causes all sorts of headaches.
Got it, but qeustion regarding clock
So I used clocking wizard in a test proejct and was able to generate clock as well (from 66MHz crystal converted to 10MHz crystal and checked the LSB of 23 bit counter...
)
Now I have this question...
On what basis should I select BUFG, BUFH, BUFGE, no buffer etc...
Also how should what should I put in place of
Input jitter value since I don't know what jitter the oscillator clock or external clock is going to give ...?
@Vonn..Sir I tried Chipscope as well earlier for simulation but had problems, I guess I did not instantiated cores and expected unexpected
, but will definitely try it again. Thanks