andrew257
Member level 2

module sine_cos
Hi All
i am after some code to simulate a sinewave input. It will be used as part of a system to simulate the input of a ADC. None of the code has to be synthesizable.
I have found some code on this forum but i am having a hard time understanding what it does etc. If anyone could expalin it to me that would be great.
Heres the code
module sine_cos(clk, reset, en, sine, cos);
input clk, reset, en;
output [7:0] sine,cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
always@(posedge clk or negedge reset)
begin
if (!reset) begin
sine_r <= 0;
cos_r <= 120;
end else begin
if (en) begin
sine_r <= sine;
cos_r <= cos;
end
end
end
endmodule // sine_cos
To make a testbench for this code am i right in thinking i will need to generate another module for clk or can it be done with a loop?
Thank You
Andrew
Hi All
i am after some code to simulate a sinewave input. It will be used as part of a system to simulate the input of a ADC. None of the code has to be synthesizable.
I have found some code on this forum but i am having a hard time understanding what it does etc. If anyone could expalin it to me that would be great.
Heres the code
module sine_cos(clk, reset, en, sine, cos);
input clk, reset, en;
output [7:0] sine,cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
always@(posedge clk or negedge reset)
begin
if (!reset) begin
sine_r <= 0;
cos_r <= 120;
end else begin
if (en) begin
sine_r <= sine;
cos_r <= cos;
end
end
end
endmodule // sine_cos
To make a testbench for this code am i right in thinking i will need to generate another module for clk or can it be done with a loop?
Thank You
Andrew