Simulation after synthesis

[Patok]

Hi,

I designed and synthesized a module in Verilog using Design Compiler and I obtained a netlist using a technology library.

Now I want to simulate it with either VCS or another program but I don't know the way. I tried saving my synthesized module as Verilog format but VCS ask for gates of the technology library (this is a ".db" file, and I can't find a command to include this format).

How can I include the technology library? or is there another way to simulate a synthesized circuit?

Thanks in advance

 

[nikhilindia85]

u wl get a synthesized verilog netlist after synthesis with .v extension
u need this .v netlist and verilog models of ur technology library to do the post synthesys simulation.u can do this simulation in any smulator like modelsim,NC,VCS...etc
frst u compile the verilog models of technology library and then compile and simulate the netlist.before that u have to look for the verilog models of the library

 

[kaustubh]

Here is how i went about it :
1) write RTL and test bench
2) synthesize RTL and generate netlist in .v format.
3) compile the netlist, testbench and technology library (all in .v format).

The technology libary however is different from the one you would have used while doing synthesis (which would have been in .db format).

 

[Patok]

so do you know how I can get a technology library in .v format? I only have the .db file. I tried to convert the tech library into .v using write_lib on dc_shell but I couldn't, it's not supported.

 

[shiv_emf]

vcs or ncverilog will accept .v technology file.

ur vendor will provide .db and .v tech files..
pls search for it..

 

[visualart]

U may find the technology for the simulation from the verilog path.
the synopsys path (.db):
./synopsys/*.(s)db
tje simulation module path(.v):
./verilog/*.v

 

[atena]

The library .v format is nothing but the major Verilog code including those " `celldefine ", and "primitives" for the technologicl cell you use in link and target library. If you cant find the .v lib file you can write it yourself, but remember to match the pin direction with the technical lib ....