sampham04
Junior Member level 2
Hi,
I normally work with Verilog, but I have a design and testbench in VHDL. Can anyone provide me with a script of how to simulate the VHDL code with Synopsys VCS?
Thank you!
I normally work with Verilog, but I have a design and testbench in VHDL. Can anyone provide me with a script of how to simulate the VHDL code with Synopsys VCS?
Thank you!