aarthy_maya
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Simulating Custom Verilog Modules with Cadence AMS simulator
Hi Everyone,
Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock.
I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design.
I have verified the decoder separately for its functionality using ideal voltage sources and it works well.
Problem : When I try to use the test bench written in verilog to generate the input to the decoder, the simulation yields no output even though it completes successfully.
Simulator: I have tried both AMS with Ultrasim Solver or AMS with Spectre Solver, I also have connect modules included in the simulation.
Is there anything I am missing to see/include?
Thanks!
Aarthy
Hi Everyone,
Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock.
I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design.
I have verified the decoder separately for its functionality using ideal voltage sources and it works well.
Problem : When I try to use the test bench written in verilog to generate the input to the decoder, the simulation yields no output even though it completes successfully.
Simulator: I have tried both AMS with Ultrasim Solver or AMS with Spectre Solver, I also have connect modules included in the simulation.
Is there anything I am missing to see/include?
Thanks!
Aarthy
Last edited:
