vlsi_student
Newbie level 4
Hello every one
I used synopsys DC for synthesis with the option of clock gating .. now i want use model sim for gatel level netlist simulation. can some one please tell as how to proceed .. r please give soem materials which gives info abt this ..
thnks a lot in advacne
sing
I used synopsys DC for synthesis with the option of clock gating .. now i want use model sim for gatel level netlist simulation. can some one please tell as how to proceed .. r please give soem materials which gives info abt this ..
thnks a lot in advacne
sing