simulate the rejection effect to power supply

[iscmos]

rejection of glitch

I want to simulate the rejection effect to power supply. for example, if there is a glitch in power supply, and ideally I don't want it affect the system, the problem is how to define this glitch, I mean what's the reasonable time period for the glitch? Is 1us a little long? In order to reject this glitch, resistor and capacitor are used as a filter. and is there some other options?

 

[saro_k_82]

Re: rejection of glitch

The best thing to do is to subject the supply to glitches it is most likely to see in the real case. Add inductors from the package model..overestimate it a little bit. Add a switched current source in parallel drawing current from the supply (to model other blocks in the chip).

 

[iscmos]

Re: rejection of glitch

The best thing to do is to subject the supply to glitches it is most likely to see in the real case. Add inductors from the package model..overestimate it a little bit. Add a switched current source in parallel drawing current from the supply (to model other blocks in the chip).

Hello saro_k_82, Thanks for your help, to simplify the case, I change voltage source from constant voltage to vpwl voltage source. I don't exactly understand what do u mean? Sorry, could you explain it more precisely? Thanks!

 

[saro_k_82]

Re: rejection of glitch

Change the parameters to suit your circuit. Have a constant voltage source.