Natural mismatch ought to be in the tens of mV, FET:FET. Autozero
takes out some portion of the lineup mismatch rollup; the back end
offsets are only divided by front end gain, so some residue ought to
be seen.
If you are able to run a single MC iteration (look at the Vio result
and find the worst case iteration, and rerun that "standalone" with
MC functionality enabled) then you could debug the "bad actor".
This could be a circuit problem, some devices not being corrected.
It could also be insane statistics, which of course your CAD folks
will never admit to, but you could prove if you dug deep enough.
If (say) you found one transistor whose .OP VT was 100mV out
from the rest, you might call it a "point defect" rather than a
normal mismatch and negotiate it away, at design review, on that
basis. Been down that road once or twice, models are not to be
blindly accepted (especially when everybody has piled on their own
statistical sandbagging with no thought to the rollup result, vs fab
capability).