Simulate the offset of a comparator

[liqiyue]

When I simulate the comparator offset, what percentage of input diff pair mismatch should be set?
And what is the typical value of offset when using TSMC 0.18um technology?
Thanks!

 

[erikl]

When I simulate the comparator offset, what percentage of input diff pair mismatch should be set?

This depends on the W*L gate area. Search for "pelgrom + mismatch".

And what is the typical value of offset when using TSMC 0.18um technology?

Typ. 10mV, max. 20mV, s. the TSMC 0.18um lot-to-lot statistics below.

 

[aryajur]

Hi liqiyue,
The mismatch model of the transistors should be added in the transistor models so that monte Carlo simulation would be able to use that data and generate your mismatches and offsets. If its not there in the models provided (although TSMC provides mismatch data in their models) then adding them on your own you need to add the sigmas for Vth variation and tox variation for lot to lot variation. This would require careful work. But I assume your models should have the data.
If the models have the data then you simply need to run the Monte Carlo to find out the offset. "Typical" offset for a comparator is not something you can say, since it would depend on the comparator topology and the size of devices and the type of devices you use and the current you use in the comparator and would vary widely. I guess you wanted to know the typical vth mismatch in the process? For that you can either look at the model file sigma and multiply it with sqrt(2) or look at their process data which I think erikl attached.

 

[liqiyue]

Thanks, I'll have a look at monte carlo simulation.

And, erikl, Thank you for you statistics file.