Simulate DRAM on modelsim

[nsgil85]

Hi all,

I'm trying to build a semi generic dual clock fifo which include B-RAM resource (spartan-6 or cyclone IV) and control unit.
I was able to synthesis the B-RAM (using ISE) but didn't get the idea how to simulate this resource in Modelsim(10.4a).

Thanks

 

[dpaul]

It is useless to synthesize a design before verifying its functionality. In order to do this you need to write a test-bench that will simulate your design. Best would be a self-checking test-bench which apart from writing in and reading from the FIFO, should also test its overflow and underflow conditions.

 

[nsgil85]

Hi dapul,

I wrote test-bench for this fifo, but unfortunately i couldn't get Modelsim simulate it because it uses spartan-6 b-ram resource which is not recognized by.

How do i "tell" Modelsim to compile this resource?

Gil

 

[ads-ee]

You have to compile the Xilinx HDL libraries to simulate a design that contains primitives. ISE has a compxlib command or use the GUI and the compile simulation libraries menu option.

See page 321 of this to use compxlib.
This describes compiling using the ISE GUI.