promach
Advanced Member level 4
1) For table 1 of Berkelay Paper , why "Input must be valid for at least two clock periods in the new domain." ?
The explanation:
Could anyone tell why it has to do with hold time of the first synchronizer flip-flop ?
2) For pulse synchronizer or what we known as toggle synchronizer, I do not understand the explanation highlighted in yellow that is given below:
The explanation:
Could anyone tell why it has to do with hold time of the first synchronizer flip-flop ?
2) For pulse synchronizer or what we known as toggle synchronizer, I do not understand the explanation highlighted in yellow that is given below: