Simple question on a 2 input bus multiplexer in Verilog

[bciaren]

I'm trying to learn Verilog over the summer and I'm running into trouble understanding the necessity of having a 4-bit bus. My understanding of it is that it behaves like a wire. Why can't one bit of in_3 being high for example, be enough for the other 4 gates? Why do we need to replicate it four times for it to work? Here is the block diagram followed by the code from "Verilog by Example" book.

module bus_sigs
  (
  // Inputs
  in_1,
  in_2,
  in_3,
  // Outputs
  out_1
  );
  
// Port Definitions

input  [3:0]  in_1;
input  [3:0]  in_2;
input         in_3;

output [3:0]  out_1;

wire   [3:0]  in_3_bus;

// ------Design----------

assign in_3_bus = {4{in_3};
assign out_1 = (~in_3_bus & in_1) | (in_3_bus & in_2);

endmodule

 

[dave_59]

Because the example is trying to model the exact gate-level equations so they are using the bit-wise AND operator '&' , not the logical AND operator '&&'. Learn the difference between bit-wise and ;lgical operators in the LRM

If you wanted to model this at a higher RTL style, you would do

assign out_1 =in_3 ? in_2 : in_1;