[SOLVED] Simple code not working

[bareil76]

Hi All,

I have a simple code running in a Spartan 6 device. I can flash leds and everything works fine.

I have the following peice of code. Where Tx_mac_wa is always 0

I have verified
1)Clk_SYS is workin
2) Tx_Hwmark_pl is 9
3) Tx_Lwmark_pl is 8
4) Fifo_data_count is 0

always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Tx_mac_wa   <=0;  
    else if (Fifo_data_count>=Tx_Hwmark_pl)
        Tx_mac_wa   <=0;								//then...Tx_mac_wa  will  be  asserted  0  to  tell  user  application  to  hold  packet  transmitting./
    else if (Fifo_data_count<=Tx_Lwmark_pl)
        Tx_mac_wa   <=1;

Am I missing something?

 

[bking]

Since you didn't list it under things you've verified, what is the Reset doing?

 

[bareil76]

Good point.

The reset is setting everything to 0. Then I verified that Tx_Hwmark = 9 and Tx_Lwmark =8.

always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin 
        Tx_Hwmark_pl        <=0;
        Tx_Lwmark_pl        <=0;    
        end
    else
        begin 
        Tx_Hwmark_pl        <=Tx_Hwmark;
        Tx_Lwmark_pl        <=Tx_Lwmark;    
        end

 

[ads-ee]

The point bking was making is: have you verified reset goes from a 1 to a 0 at some point in time and that you are looking at the *_pl outputs after reset is 0.

 

[bareil76]

Yes I have verified that reset goes from 1 to 0.

If I change Tx_Lwmark to a parameter instead of an input it works!

So the problem was with Tx_Lwmark which could be change in another module by this...

always  @(posedge Reset or posedge Clk)
    if(Reset)
        RegOut      <=RegInit;
    else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])    ///Si writeEnable is set AND chipSlect is enabled AND CA_reg[7:1](Addr of external) ==CA_reg_set[6:0] (addr of internal)
        RegOut      <=CD_in_reg;             //update the register value

where CA_reg_set, CA_reg, CCSB and CWR_pulse are all UNCONNECTED signals.

If I change the above to this

always  @(posedge Reset or posedge Clk)
    if(Reset)
        RegOut      <=RegInit;
    else
        RegOut		  <=RegInit;

What does that tell me ???? My reset is wrong or RegOut <=CD_in_reg; was evaluated in some way??

 

[ads-ee]

Out of context code snippets is not the best way to show us what you've got connected.

Regardless, You state that the following signals are unconnected:

where CA_reg_set, CA_reg, CCSB and CWR_pulse are all UNCONNECTED signals.

If they are unconnected then everything that uses those signals will be assigned a default value (usually 0) and logic reduction will occur. So in all likely hood the RegOut value was removed or is generating a constant 0.

If you want to synthesize a design you should have all your logic implemented otherwise the tools will remove anything that isn't driven.