Simple-but-worthwhile stability check for SMPS feedback loop?

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treez

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Hello,
In a current mode flyback, compensated with a type 2 error amplifier, it is a fact that the error amplifier's high frequency pole should always be at a lower frequency than the frequency of the power stage ESR zero...ie in order to assure you avoid instability

Is this true?
ie, ensuring the above won't assure stability but is a good and worthwhile check to do, because if the error amplifier's high frequency pole is above the esr zero in frequency,then that is bad and could well lead to instability.

ESR zero = 1/(2.pi.R.C)
....where R = ESR and C = C(out)


Error amp high frequency pole is 1/(2.pi.R.C) where R = Top output divider resistor and C = the low value cap from output to input of the opamp
 

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