Stability of Buck SMPS with added output capacitance

[cupoftea]

Hi,
We are just about to do a Buck for 24vin, 15vout and 3Aout.
We want to evaluate difference between voltage mode control and current mode control.
We want as little output capacitance as possible, occupying as small area as poss on the board.
But the customer may attach a product with high amount of input capacitance. So we need it to stay stable
in this case.
Obviously we will go through and calculate the bode plots, using the expressions for power stage gain/phase, and
error amp gain/phase (+modulator)...and we will see which is more stable as output capacitance is added.
The calcs will take a good few hours in excel.....can you spoil it for us and tell us which control
method is going to mean more conducive to extra added output capacitance?

 

[crutschow]

There is no "off the top of my head" answer without analyzing the actual regulator circuits. but you can add an inductor at the supply output to basically isolate the control loop from the added load capacitance so it has little effect on the control-loop stability.
The added inductor will also reduce any output ripple voltage.

 

[cupoftea]

Thanks, but as can be seen from page 10 onwards of the following...

Hangsek choi doc

......"Practical Feedback Loop Design Considerations for
Switched Mode Power Supplies"

When an LC filter is added to the output of an SMPS, the control loop is further complicated, and the additional calculations listed at page 10 onwards are then needed to re-calculate the gain and phase margins.

IMHO , i believe that the current mode design will "generally" be more amenable to the addition
of extra output capacitance whilst remaining stable.
This is because the voltage mode design will have a double pole in the power stage output,
and when output C is increased, then the output filter poles get lower in frequency.
However, at the same time, increasing the Cout, is likely to reduce ESR out..
So therefore, overall , i would predict the ESR filter zero will get higher in frequency,
and this i fear, will be the demise of stability of the voltage mode design, as its Cout is increased.

 

[D.A.(Tony)Stewart]

Current feedback gives 1st order feedback on current gain. Voltage is 2nd order with low margin. RC lead-lag margin vs ripple spec depends on having some 1st order voltage feedback cause by ratio of Rout/ESR or real(source/load) impedance ratios. This means there is a obvious tradeoff for step response error and impedance ratios. Negative feedback gain lowers the effective Rout from open loop RdsOn , Rd etc. Rout/load=1/ load regulation error x100%.

With complete design specs, you cannot choose an optimum design.

 

[D.A.(Tony)Stewart]

Current mode feedback is the only way to ensure stability with infinite capacitance load.

Imagine if the load ESR was zero , there would be no 1st order voltage feedback ripple and only integral of current ripple, which reduces phase margin by 90 deg such that if you only had 45 to 60 deg. margin to start with, it would be unstable at some pulse loads.

 

[crutschow]

Thanks, but as can be seen from page 10 onwards of the following...

Hangsek choi doc

......"Practical Feedback Loop Design Considerations for
Switched Mode Power Supplies"

When an LC filter is added to the output of an SMPS, the control loop is further complicated, and the additional calculations listed at page 10 onwards are then needed to re-calculate the gain and phase margins.

I wasn't clear.
My suggestion was to put the second inductor after the feedback loop connection, not inside it, so it has little effect on loop stability.

 

[cupoftea]

Thanks, i understand, ..though that still does have effect on stability unfortunately...the Choi doc ref'd above being needed to re-calc the gain and phase margins.