kiranvaddireddy
Newbie level 2
Hello,
The ATPG patterns I've delivered are failing in transition test (TFT) mode. All stuck-at patterns have passed and also Transition chain test passed. We've run OCC domain based patterns to check which OCC is causing the issue. Now, TFT patters are failing only in 1 particular OCC domain. All the other OCC clock domains patters have passed.
This particular OCC patterns are failing in normal voltage conditions, but are passing in High voltage conditions. Assuming Local IR drop(hotspot) is the issue, we ran low power patterns which has less toggling rate(switching activity) than functional mode. Those patterns are also failing in normal voltage and passing in High voltage condition.
I've checked timing on the failing flops, which I got by running internal mode (compression bypass) patterns. It was pretty clean. All those flops have around 500ps positive slack. What could be reason behind these failures?
Thanks,
Kiran
The ATPG patterns I've delivered are failing in transition test (TFT) mode. All stuck-at patterns have passed and also Transition chain test passed. We've run OCC domain based patterns to check which OCC is causing the issue. Now, TFT patters are failing only in 1 particular OCC domain. All the other OCC clock domains patters have passed.
This particular OCC patterns are failing in normal voltage conditions, but are passing in High voltage conditions. Assuming Local IR drop(hotspot) is the issue, we ran low power patterns which has less toggling rate(switching activity) than functional mode. Those patterns are also failing in normal voltage and passing in High voltage condition.
I've checked timing on the failing flops, which I got by running internal mode (compression bypass) patterns. It was pretty clean. All those flops have around 500ps positive slack. What could be reason behind these failures?
Thanks,
Kiran