Significance of " MOS transistor Ring structure"

enclosed transistors

Yarrow said:

erikl said:

Yarrow said:

The extracted drain area is (ad=) 2.6861 in that particular case. But when measured manually, it's about 50% smaller.
The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

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How can the perimeter of any area ≠ 0 be 0 ?

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I am sorry, its my english that has gone bad. "ps" and "pd" dont stand for source/drain perimeter, the correct term is periphery.The green line distanse in the attached file is the periphery of the source/drain in the linear transistor. (0.23+6.0+0.23 = 6.46)

Apperently the periphery in Cadence is handeled like the outer edge of an object.

Click to expand...

Not a Cadence but a "rule writer". Are you sure he is right?
BTW, as I remember (may be it is not correct) that the Spice simulator has an option which defines how to consider the device perimeter - with or without the transistor width.
Moreover, may be if you define device pd/ps as 0, simulator substitutes it with some default value?

Yarrow said:

Anyways, I think the right way to go is 3D CAD tools using finite-element-method (FEM). At the moment I am trying to aquire such a tool (Synopsys Sentaurus TCAD) to provide me with more accurate simulation results. Hopefully the CAD tool can be integrated with Cadence to enable for simulations on bigger cells then ones only containing a couple of transistors.

Click to expand...

Im affraid you wont get any correct information on device 3D profile from fab if you dont have a direct access to technology/model information (if you are not a member of the fab's design support or technology team, for ex.)

But as I know some fabs have a special models for ring transistors.

po2act

sdedov said:

Yarrow said:

erikl said:

Yarrow said:

The extracted drain area is (ad=) 2.6861 in that particular case. But when measured manually, it's about 50% smaller.
The drain perimeter is 0, and that is the only extracted parameter that is extracted correctly.

Click to expand...

How can the perimeter of any area ≠ 0 be 0 ?

Click to expand...

I am sorry, its my english that has gone bad. "ps" and "pd" dont stand for source/drain perimeter, the correct term is periphery.The green line distanse in the attached file is the periphery of the source/drain in the linear transistor. (0.23+6.0+0.23 = 6.46)

Apperently the periphery in Cadence is handeled like the outer edge of an object.

Click to expand...

Not a Cadence but a "rule writer". Are you sure he is right?
BTW, as I remember (may be it is not correct) that the Spice simulator has an option which defines how to consider the device perimeter - with or without the transistor width.
Moreover, may be if you define device pd/ps as 0, simulator substitutes it with some default value?

Yarrow said:

Anyways, I think the right way to go is 3D CAD tools using finite-element-method (FEM). At the moment I am trying to aquire such a tool (Synopsys Sentaurus TCAD) to provide me with more accurate simulation results. Hopefully the CAD tool can be integrated with Cadence to enable for simulations on bigger cells then ones only containing a couple of transistors.

Click to expand...

Im affraid you wont get any correct information on device 3D profile from fab if you dont have a direct access to technology/model information (if you are not a member of the fab's design support or technology team, for ex.)

But as I know some fabs have a special models for ring transistors.

Click to expand...

Hi

I havent played around with this structure in a while. I have desided to base my design on linear transistors since there are so many uncertainties around the ring structure and CAD tools.

Furthermore I will try to somewhat counter the Total Ionizing Dose (TID) effects with reverse body bias (RBB). Perhaps not very practical, but it will perhaps be interesting to get some experimental results.

When it comes to the extracted parameters, your right, it makes sence that the "rule writer" dertermines the extracted parameters. However, ps/pd seem to be calculated as peripheries, and not perimeters. (according to the current rules file) This becomes appearent when comparing linear and ring transistors. (Although I am not 100% sure, I never am )

I have also looked at the rules file and a old spice model file, and what i "concluded" from that was that their were to many constraints for me to start messing around with. Even if I found the right lines to change, I would still not be sure that I am getting correct simulation results. Therefore I did not do anything.

Actually, I also think that getting tech-info from the fab might be hard, to say the least. The often used reason is that the university is to "open". However, the head engeneer at our group seemed optimistic. So I am hoping that it will be possible to sign som kind of agreement that enables for temporary info. Anyways, i cross my fingers :S