superhet
Junior Member level 3
verilog addition
im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow?
the above simulation gives me 127+127=-2
can somebody help??????????
im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow?
Code:
module stimulus;
reg signed [7:0] a,b;
wire signed [7:0] c;
signed_adder my_adder(a,b,c);
initial
begin
$monitor($time, " a = %d, b = %d, c = %d", a, b, c);
end
initial
begin
a = 127; b = 127;
end
endmodule
module signed_adder(a,b,c);
input signed [7:0] a,b;
output signed [7:0] c;
assign c = a+b;
endmodulethe above simulation gives me 127+127=-2
can somebody help??????????