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signals between entities in VHDL

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alexz

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when I have number of entities where 2 of them are instantiated in 1.
There is an output from a 1 is instantiated to the input of another through a signal in a top level.
How should that be in terms of in/out declaration of that signal?

port map (mysignal => outsignal, ...

port map (mysignal => insignal, ...


eventially the outsignal should be connected to the insignal.
If I declare the insignal as an input and the out signal as an output in these entities, it does not work.

basically, it suppose to be an address decoder.
where the outsignal is an output from the decoder, which goes to the input of a peripheral
 

kgeorge123

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First of all I am not sure if you have instantiated the two entities in the top level entity.
Before doing portmapping you need to instantiate as a component and then portmapping the signals will do the job. You will have to create a third signal say X

and then

Portmap(Input signal => X)
Portmap(output signal =>X)

Signals are just like wires inside the top level entity.And you cannot portmap ports of entities without instantiating them as a component.
 

alexz

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That is exaclty the way I am doing it, but it does not work because in thefirst entity, the signla is out, but in the second the signal is in.
Theere is an intermidiate signal in the top level as well.
 

vivek

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r u getting any errors while compiling ur code? if so please give the error message then it will be easy to pick out the error. Basically what u told is right, it should work. may be there is a simple mistake in the code.
 

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