Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

signal routing using clock framework

Status
Not open for further replies.

ssankurathri

Full Member level 3
Joined
Mar 16, 2006
Messages
186
Helped
14
Reputation
28
Reaction score
5
Trophy points
1,298
Location
Bangalore
Activity points
2,401
Hi,

I have an internal signal in fpga. This internal signal, I would like to use it as clock. so, want to route it using the clock framework of fpga there by reducing the skew.
what attributes I can use on this signal to make sure that FPGA treats it as clock.

Regards
skr
 

sharath666

Advanced Member level 2
Joined
Apr 4, 2011
Messages
552
Helped
126
Reputation
252
Reaction score
124
Trophy points
1,323
Location
India
Activity points
3,830
I understand that you need to constrain it correctly..
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,065
Helped
2,077
Reputation
4,171
Reaction score
2,030
Trophy points
1,393
Activity points
39,112
As long as all logic that uses this clock are registers, and you only use the signal as a clock, the synthesisor should place this signal on the clock network automatically.
 

ssankurathri

Full Member level 3
Joined
Mar 16, 2006
Messages
186
Helped
14
Reputation
28
Reaction score
5
Trophy points
1,298
Location
Bangalore
Activity points
2,401
Thanks.
synthesizer hasn't routed it on clock network. so, I want to use constraints.
plz guide me in using correct constraints/attributes.

Regards
skr
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,065
Helped
2,077
Reputation
4,171
Reaction score
2,030
Trophy points
1,393
Activity points
39,112
If it hasnt routed it this way, then I suggest that you're not using it properly. It should NOT be the output from logic, as logic generated clocks can be unreliable. You can force them on to clock networks, but it is not recommended.

Why not post the code, as I suggest this is the main problem.
 

ssankurathri

Full Member level 3
Joined
Mar 16, 2006
Messages
186
Helped
14
Reputation
28
Reaction score
5
Trophy points
1,298
Location
Bangalore
Activity points
2,401
Thanks.
it is a gated clock. you are right. The logic generated clocks can be unreliable.
can u plz tell me why it is not recommended to force them on to clock networks? and how to force them on to clock networks?

Regards
skr
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,065
Helped
2,077
Reputation
4,171
Reaction score
2,030
Trophy points
1,393
Activity points
39,112
Logic clocks are not recommended because they they are liable to problems from P&R and PVT variations. So Logic clocks should not be generated in FPGAs.
The P&R can sometimes put in on the network automatically, but You can also force it - but Ive never done it myself.

From my understanding this should be a final resort. Why is it a logic clock? why cant it be a clock enable?
 

ssankurathri

Full Member level 3
Joined
Mar 16, 2006
Messages
186
Helped
14
Reputation
28
Reaction score
5
Trophy points
1,298
Location
Bangalore
Activity points
2,401
Thanks. it is Xilinx. can I use BUFG primitive on this internal signal, as it is not a input pin?
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,820
Helped
1,811
Reputation
3,632
Reaction score
1,772
Trophy points
1,393
Location
USA
Activity points
59,025
Yes, you can, but as Tricky has pointed out it is not recommended. Each time you build the design it may move the source of the clock to another location and the timing will change. If you desire consistent results then you will have to use placement constraints.

It is always better to use clock enables instead of generated clocks in an FPGA. Unless you are doing an ASIC emulation that has internally (non-PLL) generated clocks and gated clocks, then there aren't any good reasons to be doing this in an FPGA.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top