signal routing using clock framework

[ssankurathri]

Hi,

I have an internal signal in fpga. This internal signal, I would like to use it as clock. so, want to route it using the clock framework of fpga there by reducing the skew.
what attributes I can use on this signal to make sure that FPGA treats it as clock.

Regards
skr

 

[sharath666]

I understand that you need to constrain it correctly..

 

[TrickyDicky]

As long as all logic that uses this clock are registers, and you only use the signal as a clock, the synthesisor should place this signal on the clock network automatically.

 

[ssankurathri]

Thanks.
synthesizer hasn't routed it on clock network. so, I want to use constraints.
plz guide me in using correct constraints/attributes.

Regards
skr

 

[TrickyDicky]

If it hasnt routed it this way, then I suggest that you're not using it properly. It should NOT be the output from logic, as logic generated clocks can be unreliable. You can force them on to clock networks, but it is not recommended.

Why not post the code, as I suggest this is the main problem.

 

[ssankurathri]

Thanks.
it is a gated clock. you are right. The logic generated clocks can be unreliable.
can u plz tell me why it is not recommended to force them on to clock networks? and how to force them on to clock networks?

Regards
skr

 

[TrickyDicky]

Logic clocks are not recommended because they they are liable to problems from P&R and PVT variations. So Logic clocks should not be generated in FPGAs.
The P&R can sometimes put in on the network automatically, but You can also force it - but Ive never done it myself.

From my understanding this should be a final resort. Why is it a logic clock? why cant it be a clock enable?

 

[std_match]

Is this for Xilinx or Altera? For Xilinx, try to drive the clock with the BUFG primitive. For Altera, try to use the "Assignment Editor". Look at AN307, page 29, "I/O Buffer Conversion":
https://www.altera.com/en_US/pdfs/literature/an/an307.pdf

 

[ssankurathri]

Thanks. it is Xilinx. can I use BUFG primitive on this internal signal, as it is not a input pin?

 

[ads-ee]

Yes, you can, but as Tricky has pointed out it is not recommended. Each time you build the design it may move the source of the clock to another location and the timing will change. If you desire consistent results then you will have to use placement constraints.

It is always better to use clock enables instead of generated clocks in an FPGA. Unless you are doing an ASIC emulation that has internally (non-PLL) generated clocks and gated clocks, then there aren't any good reasons to be doing this in an FPGA.