'signal connected to multiple drivers' problem

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serhannn

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Hi. We are trying to code a sort of accumulator in Verilog, but when we write the code below, we get an error saying that "this signal is connected to multiple drivers" for every signal that even does not appear in the expression below. For example, we also have a register "N" and we get the same error for it, too.

Code: 
sum_temp=(a + k*dx - dx_half)*(a + k*dx - dx_half)+m*(a + k*dx - dx_half)+nn;
sum=sum+sum_temp;

Does anybody know the reason for this error? Thanks a lot for your help.
 

perhaps you have "if N = 5" instead of "if N == 5" someplace.
 

Try to put the complete code, It will be easy to identify the error/bug in your code.
 

u can use swith,ff... to avoid multiple drivers' problem
 

Usually this happens when the signal N is assigned values in different processes

like in VHDL (I'm not very familiar with Verilog)
Code: 
process1:process(clk)
begin
   if rising_edge(clk) then
      N <= some_value;
      ...
end process;

process2: process (clk, ...)
begin
   if rising_edge(clk) then
      N <= some_other_value;
      .....
end process;
 

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