hi guru59,
In Verilog, whether the choice is a signal or variable will depend on:
(1) wire or reg is used
(2) always or assign is used
For example, a variable would look like this:
reg Y;
always Y <=1;
//This is called Non Blocking Procedural Assignment Statement.
//But it is only possible inside an Initial statement.
//Likewise, it is a variable can only be used inside a Process statement.
For example, a signal would look like this:
wire n;
assign n=1; //Note that wire is only used for in or inout. Never for output because wire is for reading, not latched or registered for output.
Alternatively,
reg Y;
always @(posedge clock) Y=1;
//In this case, reg is output signal which is registered or latched.