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Signal and Variable ....in VERILOG

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Guru59

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hai.

i am NOVICE in verilog.i need to know how to declare SIGNAL and VARIABLE in Verilog...

thanks in advance
 

aji_vlsi

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Guru59 said:
hai.

i am NOVICE in verilog.i need to know how to declare SIGNAL and VARIABLE in Verilog...

thanks in advance
Guess you come from VHDL background, in Verilog just use "reg" datatype and use blocking and non-blocking assignment. Roughly a variable is like a reg with blocking assign and SIGNAL behavior is mimiced using reg and non-blocking.

Do a quick google search, there are tons of Verilog material available in the net. If you require a jump start, hands-on training in Verilog, send an email to cvc.training@gmail.com

Good Luck
Ajeetha, CVC
www.noveldv.com
 

SkyHigh

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hi guru59,

In Verilog, whether the choice is a signal or variable will depend on:
(1) wire or reg is used
(2) always or assign is used

For example, a variable would look like this:
reg Y;
always Y <=1;
//This is called Non Blocking Procedural Assignment Statement.
//But it is only possible inside an Initial statement.
//Likewise, it is a variable can only be used inside a Process statement.

For example, a signal would look like this:
wire n;
assign n=1; //Note that wire is only used for in or inout. Never for output because wire is for reading, not latched or registered for output.

Alternatively,
reg Y;
always @(posedge clock) Y=1;
//In this case, reg is output signal which is registered or latched.
 

Guru59

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Thanks for that aji and Skyhigh........

does anyone of you can upload any material regarding blocking and non-blocking statements.............
 

anishrai

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Search for the book " verilog HDL...a guide to digital design and synthesis" by samir palnitkar......its a good book...
 

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